Years of engineering experience
Hello! I’m
Dhruv
Patel
Iowa State University
I study
Computer Engineering
Embedded systems · Digital design · Intelligent tools
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VLSI Design+Analog IC Design+
Circuit Design+FPGA Development+
Embedded Systems+Computer Architecture+
RISC-V Architecture+Machine Learning+
VLSI Design+Analog IC Design+
Circuit Design+FPGA Development+
Embedded Systems+Computer Architecture+
RISC-V Architecture+Machine Learning+
01 About
Curious by nature.
Precise by design.
Driven by my interest in computer engineering and my experience as an undergraduate research assistant, I enjoy applying the knowledge gained through my coursework to real-world challenges.
Through research and hands-on projects, I have strengthened my ability to analyze complex problems, explore practical solutions, and turn technical ideas into working systems that create meaningful impact.
GPA at Iowa State University
Engineering and research projects
02 Education
Built on a strong
academic foundation.
An interdisciplinary academic journey connecting computer science, computer engineering, and cybersecurity across two universities.
Aug. 2025 — Present
Iowa State University
B.S. Computer Engineering · Cyber Security Minor
Ames, Iowa · GPA 3.73/4
Relevant coursework
Integrated Circuits · Embedded Systems · Computer Organization & Architecture · Cyber Security Fundamentals & Tools · Electric Circuits & Systems
Jul. 2023 — Jun. 2025
Nirma University
B.S. Computer Science
Ahmedabad, Gujarat, India · GPA 8.5/10
Relevant coursework
Data Structures · Operating Systems · Software Development Practices · Algorithms · C · Java
03 Experience
Researching &
teaching by doing.
Hands-on engineering research and technical mentorship at Iowa State University.
May 2026 — Present
Undergraduate Research Assistant
Iowa State University · Ames, IA
Developing robust electronic systems to monitor animal health, lameness, body mass, and body composition.
Jan. 2026 — Aug. 2026
Undergraduate Teaching Assistant
Iowa State University · Ames, IA
Guide students in designing, implementing, and debugging digital logic circuits using Verilog, FPGA development tools, simulation, and hardware testing.
May. 2026 — Aug. 2026
Student Fund Raiser · Iowa State University Foundation
Iowa State University · Ames, IA
Raised funds for scholarships and student programs by engaging with alumni and donors, promoting the university's mission, fostering a sense of community, and building connections and networking with alumni.
04 Selected Projects
Engineered with
purpose.
Projects that combine research, real-time systems, and practical problem solving.
01 / Research · In-Progress
Handheld Lameness Detection Circuit for Cows
Designed and implemented force plates installed under automatic milking machines to measure the weight distribution of cows. Applied a machine learning model to detect lameness by identifying the lame leg and assigning a lameness score, enabling early intervention and improved animal welfare.
02 / Autonomous Systems · In-Progress
Hand Gesture Controlled Quadcopter
Designing and building a custom quadcopter from scratch by integrating the flight controller, ESCs, motors, power system, and communication hardware. Developing a Python and OpenCV-based hand gesture recognition system to detect gestures in real time and translate them into flight commands for controlling the drone.
03 / FPGA Integration
FPGA Implementation of a RISC-V Processor
Developed an FPGA wrapper and supporting JTAG-based interface for the DE2-115 board to load IMEM files and execute the pipelined RISC-V processor on FPGA hardware. Contributed to updating the CPRE 381 course toolflow at Iowa State University and developing a new FPGA testing infrastructure for future course use.
CyBot · Hardware + live control interface
04 / Embedded
Remote-Operated Robotic Tank Simulation
Built a remote-controlled robotic system with ultrasonic, IR, and IMU sensors, servo control, UART and I²C communication, plus a monitoring GUI.
05 / Computer Articheture
RISC-V Processor Design
Designed and implemented a 32-bit RISC-V processor using single-cycle, software-scheduled pipeline, and hardware-scheduled pipeline architectures. Simulated and verified the designs in QuestaSim using a custom toolflow to execute assembly test programs and validate processor functionality.
06 / VLSI & Digital Design
Priority Elevator Controller ASIC Design
Designed and implemented a 4-floor priority elevator controller in Verilog using finite state machine (FSM) and register-based logic for request storage, directional scheduling, floor transitions, door control, and top-floor prioritization. Verified the design using QuestaSim and Cadence simulations, followed by synthesis and physical implementation using Cadence Genus and Innovus, including placement, routing, and DRC/LVS verification.
05 Skills
Skills I use to turn
ideas into systems.
Languages
C · C++ · Java · JavaScript · Verilog · VHDL · Assembly · SQL · Bash · HTML
Hardware
ESP32 · Arduino · MSP430 · ARM Microcontrollers · FPGA · Sensors · Actuators · TIVA-C · Raspberry-Pi
Design & Simulation
Cadence Virtuoso · QuestaSim · Quartus Prime · MATLAB · LTspice · VSCode · Code Composer Studio · Pandas · Numpy · Github
Security Tools
Nmap · Wireshark
Operating System
Windows · MacOS · Kali Linux · Ubuntu · Linux
Other Tools
Microsoft Office Suite · Google Workspace · Figma · Canva Datasheet Analysis · Schematic Interpretation · Technical Documentation · Hardware–Software Integration · System Testing · Deep Learning · Machine Learning · Neural Networks · Image Processing · Data Analysis
Have a challenge worth engineering?